1. Field of the Invention
This invention relates to an electronic circuit and, more particularly, to a buffer circuit and/or method which consumes minimal power, provides large swing voltages of a common mode output, and avoids errors on the common mode output arising from processing mismatches of dissimilar type transistors.
2. Description of the Related Art
Buffer circuits (hereinafter "buffers") are generally known as having two important applications. In many instances, buffers are used to temporarily store data, thus allowing them to compensate for differences in the flow of data or differences between the occurrence of events. Buffers can also be used to provide significant drive current to relatively high impedance load. A buffer can therefore be used as an output driver to match differences between loads placed on the input and the output of the buffer or driver. Accordingly, buffers can sometimes be thought of output drivers, and the terms hereinbelow will be interchangeably used.
Buffers can be implemented as part of an integrated circuit. For example, many integrated circuits include a core section and an input/output ("I/O") section. The I/O section may be arranged near the periphery of the integrated circuit to provide additional drive strength to signals forwarded from the integrated circuit to possibly another integrated circuit. In other examples, buffers are used possibly within the core section between subsystems to provide timing and drive strength matching between those subsystems. Regardless of its placement, a buffer can be formed as either a separate discrete element or within various portions of an integrated circuit.
In some instances, an arrangement of buffers can be used to drive an average voltage value upon a load. Referring to FIG. 1, a pair of buffers 10 and 12 are coupled to receive input voltages V.sub.A and V.sub.B, respectively. The input voltages are driven by the buffers upon a pair of resistors 14 and 16. The resistors can be of the same resistance value to assure the output voltage V.sub.OUT is near an average of the input voltages V.sub.A and V.sub.B. Buffers 10 and 12 provide unity gain and sufficient current to drive each of resistors 14 and 16 so that V.sub.OUT is representative of a midscale or average voltage value of the input voltages. For example, if V.sub.A is 3.0 volts and V.sub.B is 2.0 volts, then V.sub.OUT will be approximately 2.5 volts. The average or midscale voltage is henceforth referred to as the common-mode voltage.
As clock speeds rise beyond, e.g., 100 MHz, the advantages of using differential or complementary signals become obvious. Noise on the complementary signals is less of an issue than if the signals were not complementary since that noise is demonstrated as common-mode noise. For example, if the voltage at V.sub.OUT increases, then it can be ascertained that a positive noise spike occurs on both differential signals V.sub.A and V.sub.B. That noise can be disregarded if, for example, the complementary signals V.sub.A and V.sub.B are forwarded to a differential amplifier which amplifies a difference in complementary voltages and not a neutral or "common" change or skew.
FIG. 2 illustrates one example by which buffer 10 or buffer 12 can be implemented with metal oxide semiconductor ("MOS") transistors. For example, if the input voltage V.sub.A is placed on transistor 20, then node 22 will be one gate-to-source voltage ("V.sub.gs ") amount below V.sub.A, or V.sub.A -V.sub.gs. By definition, V.sub.gs is equal to V.sub.T +V.sub.SAT, where V.sub.T is the threshold voltage and V.sub.SAT is an additional voltage needed to place the transistor in the saturation region. In typical applications, Vgs is essentially equal to V.sub.T, especially if the transistor at issue is relatively large and therefore requires minimal V.sub.SAT amounts. If V.sub.SAT of transistors 20 and 28 are minimal or are the same, then any differences between V.sub.A .backslash.V.sub.B and the output voltage at node 30 is due essentially to V.sub.T of those transistors.
The threshold needed to turn on n-channel transistor 20 is henceforth referred to as V.sub.TN. Assuming transistors 24 and 26 are active with sufficient bias voltage (N.sub.BIAS and P.sub.BIAS) respectively, V.sub.A -V.sub.gs (or, for the reasons described above, V.sub.A -V.sub.TN) at node 22 will turn on transistor 28. Transistor 28, being a p-channel transistor rather than an n-channel transistor, produces a voltage at the output node 30 of buffer 10/12 equal to V.sub.A -V.sub.gs(N) +V.sub.gs(P). If V.sub.SAT of the transistor pairs are matched or are minimal, then the voltage at the output node 30 is proportional to V.sub.A -V.sub.TN +V.sub.TP. Therefore, it is the relative differences in n- and p-channel threshold that present a problem, as will be described below.
A typical MOS process requires the n-channel transistor regions to be processed (i.e., implanted) at a dissimilar time than the p-channel regions. This implies that the n-channel area receives not only a dissimilar type of implant but, more importantly, a dissimilar concentration and doping profile (i.e., implant depth) than p-channel areas. As a natural consequence of process differences, the threshold values of n-channel transistors do not necessarily match the p-channel transistors even though matching is warranted during design. Any mismatch whatsoever may cause the voltage at node 30 to not equal the input voltage (V.sub.A or V.sub.B). Accordingly, buffer 10/12 shown in FIG. 2 may not be a desired unity gain buffer since threshold mismatch may skew the output voltage at node 30 either above or below the input amount.
Referring to FIGS. 1 and 2 in combination, any skew whatsoever at the output of buffers 10 and 12 will correspondingly cause the equal valued resistors to skew the common-mode output V.sub.OUT. Even though it is attempted that V.sub.OUT be an average of the input voltages, threshold mismatching within one or both buffers will cause V.sub.OUT to be above or below the midscale, average or common-mode voltage value. The problem is compounded when both buffers are skewed the same amount upward or downward, leaving a common-mode value significantly higher or lower than what that value should be.
An attempt to overcome threshold voltage mismatch is shown in the unity buffer arrangement of FIG. 3. By tying one input of buffers 30 and 32 to the respective output forces the buffers to be single-ended opamps and the input voltages V.sub.A and V.sub.B to translate upon resistors 34 and 36. In applications where the differences between input voltages is desired (i.e., high speed applications), then, it would be beneficial to maintain both inputs available to receive input voltages V.sub.A and V.sub.B. Differences between those voltages can be monitored and possibly amplified as a natural outcome of the buffer or output driver.
The arrangements of FIGS. 1 and 3 are not only single-ended, but also involve a significant number of transistors and major current-carrying branches. For example, each buffer of FIG. 1, shown in FIG. 2, involves four transistors and two major current branches since the bias transistors are maintained fully on. Thus, the common-mode output produced by the circuit of FIG. 1 involves a total of 8 transistors and four major current branches between the power supply and ground. Similarly, each buffer or opamp 30/32 in FIG. 3 uses approximately 7 transistors and a minimum of 3 major current branches. This, produces a cumulative of 14 transistors and 6 major current branches needed to produce a common-mode output. Furthermore, the operating range of the opamp output is rather limited and the stability of each op-amp is compromised due to its internal feedback.
It would be desirable to produce a unity gain buffer or output driver which is not susceptible to threshold voltage mis-match between transistors of dissimilar types. The improved buffer must also be one which consumes less power than conventional buffers described above and which involves fewer transistors to achieve a higher density, less complex design. Still further, a buffer is needed which can produce fully differential outputs having unity gain from fully differential inputs. It is desirable that the outputs of the improved design have a significantly large output voltage range and therefore be more attuned to low voltage operation. Accordingly, the desired buffer must produce a consistent common-mode output voltage with fully differential inputs and outputs suitable for high speed applications and without the shortcomings described above.